The disclosure relates generally to a method and apparatus for calculating the temperature or temperature profile of one or more integrated circuits.
Stacked semiconductor chips architectures include one or more integrated circuit designs with interconnecting structures between chips and between chips and package and between package and the printed circuit board, where the interconnect structures may be placed in the vertical, horizontal or angular planes. The stacked chip architectures are built in accordance with one or more of various descriptions, such as hardware description languages, circuit netlists, mask layer descriptions, layout databases, package architectures, heatsink specifications, mechanical and electrical component descriptions, material stacks, topologies and properties, thermal management system specifications, semiconductor chip-package system specification which may include description of component chips and their interconnections. Example chip descriptions include: Verilog, VHDL, SPICE, SPICE variants such as PSpice, IBIS, LEF, DEF, GDS-II, OASIS, or other descriptions for chip designs and example package descriptions include: ADP (Advanced Package Design) format or dot MCM files, GERBA, JEDEC standard formats, XML, Spread sheet formats, CATIA, compact models (with thermal resistors and capacitances) or other descriptions for package designs.
As shown in FIG. 1, a semiconductor chip package 100 or stack may include one or more semiconductor chips 101a-e (hereinafter collectively referred to as “semiconductor chips”), such as CPU, GPU, DRAM, PHY, PLL, Micro-controllers, memory controllers, graphics controllers, DSPs, I/O, CMOS Sensors, Amplifiers, Video and Audio transmitter-receivers chips each containing transistors, resistors, capacitors, diodes and the like deposited upon a substrate and coupled via differing forms of electrical interconnects such as a plurality of wires, micro bumps 102a, bumps 102b, through-silicon-via (TSV) 102d, chip level metal, BEOL (back-end-of-line) interconnects and RDL (Redistribution Layer), Backside Metal (MB), intermediate to global interconnects and the pads, wire bonds, C4 bumps in a flip chip process, micro-bumps connecting chip to chip in Face to Face packaging, Face to Back or Back to Back configurations or interconnects (hereinafter collectively referred to as “interconnects”). The semiconductor chips and interconnects are packaged in any one or a combination of package architectures including but not limited to PoP, WLP, 3D-IC, with or without TSV, WB, and any variations and/or combinations of chip-package designs including but not limited to horizontal structures such as wire-bonding type and flip-chip type, stacked structures with interposer 101n such as wire-bonding type, wire-bonding with flip-chip, flip-chip type or stacked structures with interposer-less structures including through terminal via type, embedded structures including wafer-level-packaged chip 103 with chip on surface and full 3D embedded chip structure, die on wafer, wafer on wafer, system on silicon, system in package; multi-tier wire-bonded packaging; (hereinafter collectively referred to as “packages”).
The semiconductor chips 101 and interconnects 102 share electrical power, which generates heat and thermal gradients and hotspots develop in the interconnect structures. The gradients can range from single digit numbers to several 10s of degrees Celsius. The maximum-temperature hotspots can be in excess of the specified temperatures for acceptable performance and reliable functioning of the design.
Traditionally semiconductor on-chip interconnect reliability is analyzed in terms of MTF (median time to failure) and/or FIT (failures in time) and/or mean time between failure (MTBF). Interconnect failure mechanisms arise due to a combination of electrical and mechanical effects that are influenced by temperature, material and structural properties. To avoid this, failure manufacturing rules impose constraints on interconnect temperatures. For example due to low ILD thermal conductivity the maximum temperature hotspots in the die may be on an interconnect, where it needs to be maintained within allowable limits; in some scenarios the temperature differences (or gradients) across certain types of circuit interconnects in the design may be required to remain within specified bounds; in some scenarios the temperature on the interconnecting structures within the chips and/or between chips and/or between package and chip and/or between package and package and/or between package and board must remain within specified bounds; in some scenarios the electrical DC or AC current and/or current density and/or the temperature on the interconnect must be within certain specified bounds to avoid electromigration failure. In some scenarios thermal-stresses and strain fields of the structural components need to remain within prescribed limits so as not to have permanent deformation or fracture occur to them.
Compression stress is known to cause hillocks on interconnects which can cause short circuits; tensile stress is known to cause voids in interconnects which can lead to open circuits. In some scenarios the deformation may be elastic or plastic and/or be time dependent and/or temperature dependent such as creep deformation or fracture which may be caused by excessive stress or due to fatigue and be time and/or temperature dependent. In some scenarios the deformation may apply to any linear region, any area or to any volume of the chip-package system. Thermal stress may develop as the temperature variations within the semiconductor chips act upon their surrounding materials attempting to change their dimensions but are restrained by their structural boundaries. The magnitudes of unrestrained changes in dimensions are a function of temperature, CTE (property of the material), and dimensions of the structures. However, when the structural changes are restrained reaction forces develop as stresses within the structures causing deformation. Temperature induced problems are known to cause reliability failures in 2D chips and the problems are exacerbated by thermal coupling within the 3D stacked chip designs. For example the microbump layer has thousands of metal connections that are subjected to cyclic changes in temperature changes based on the workload and power dissipation of the semiconductor chips connected to it resulting in uneven heating and temperature gradients across the microbump material layer. The thermal stress combined with temperature values and current density of microbumps can cause electromigration and reduce the lifetime expectancy of the product. In some cases the material property may become affected increasing the electrical resistance and reducing the current flow in some of the microbumps causing the current load to be redistributed and thereby increasing the current load and temperatures in some other microbumps that can eventually cause a positive feedback loop that can lead to failure of the operating parts. Thus there is a need for interconnect thermal analysis to provide life and performance prediction of semiconductor chips and stacked chip-package products at the design stage.
Knowing temperature of interconnects (within a die and between dies) can (a) help to better estimate FIT rate and life time prediction based on reliability metrics for the product, (b) avoid costly layout changes due to overly pessimistic temperature assumptions. Narrow wires and other small scale interconnect structures require fine meshes that have large numbers (millions) of nodes and that result in time-consuming computations that require large amounts of computer memory which limit the capacity of even modern day computers. Without high resolution meshing the narrow and/or smaller-geometry interconnect temperatures cannot be accurately calculated nor can the calculated temperatures be annotated on interconnects. Interconnects can have multiple segments with each segment requiring a separate temperature value. Annotation requires calculated temperatures be located on the physical boundaries of interconnects and reported in a ASCII file or on a visual display (as in a GUI) with symbolic identity and/or physical locations and respective temperature values. In other words, the mesh based interconnect methods as it exists in current technology, are not scalable for large full chip analysis.
Additionally stacked chip interconnects vary from fine scale geometries (nanometers) to tens of microns to millimeters with different shapes ranging from rectangular to spherical and other types of structures with variations in the materials used for different types of interconnects. The number of interconnect shapes requiring analysis can be in the order of billions, each of which can represent a heat generating or conducting path. The said practical limitations in computation-time and capacity of existing interconnect thermal analysis methods constrains the analysis to small regions or grids of a large design such as on sections of semiconductor chips and/or across devices for example on power transistor circuits that can draw large currents. Moreover, the physical layout of semiconductor chips are in a different format and database which is traditionally based on GDSII and have mostly rectilinear geometries; package geometries can be different. For example, package interconnect wires may be curved and extend in three dimensions unlike those within a semiconductor chip. Known thermal solvers can provide FEA (finite element analysis) analysis on such structures but when shapes change, it would be desirable to accommodate changes in a manner that is more efficient than current thermal solver techniques. Different tools, methods and design flows between the chip and package designers are used in the respective domains for thermal analysis. In 3D stacked chip designs the chips and packages are integrated and assembled in specific architectures. The use of different analysis tools and methods for the chips and package respectively poses potential inconsistencies and inefficiencies in thermal analysis of interconnect structures.
To accurately estimate interconnect temperatures a plurality of determining factors need to be taken into account, such as: (a) self-heat which is the temperature caused by the power dissipated by that interconnect, the power can be average power, peak power, root mean square power or measured values; (b) mutual heating or cooling due to heat generated and/or conducted away from an interconnect structure, such as a wire, or other interconnect structures in the surrounding neighborhood; (c) thermal management system effects and (d) materials used in the semiconductor chip design and manufacturing that influence the heat transport paths. In the general nomenclature regarding the wire that is affected by the heating or cooling influence of others is called a victim while the influencing interconnects are called aggressors. The temperature of a victim interconnect is influenced by its location, size, shape, length, width, thickness, orientation, power density, thermal conductivity, electrical resistivity and neighboring interconnects' location, sizes, shapes, lengths, widths, thicknesses, orientations, power density, thermal conductivity, electrical resistivity topologies and also by the thermal characteristics of the semiconductor chips, package architectures and heat sinks. For example, interconnects are embedded in electrically non-conducting dielectric material to prevent short circuits. The dielectric materials are poor conductors of heat which deters heat escape from interconnects to the chip substrate and finally to the heat sinks. This causes the interconnect heat profiles to have long and gradual dissipation profiles in the horizontal plane. Coupling of heat in the vertical direction also exists. Temperature of any interconnect is thus affected by instance (or context) specific parameters within a spatial radius around the interconnect.
Thermal analysis involves solving the heat equation which can be stated in a general form by:
                                          ρ            ⁢                                                  ⁢            cv            ⁢                                          ∂                T                                            ∂                t                                              =                                    ∇                              (                                  k                  ⁢                                                                          ⁢                                      ∇                                                                                  ⁢                    T                                                  )                                      +            σ                          ,                            (        1        )            where ρ is density, Cv is specific heat capacity at constant volume; k is thermal conductivity; σ is heat generation density. In some variations the material constants may vary as a function of the temperature and dimensions of the heat conductive regions.
Those skilled in the art will appreciate that heat equations can be solved in a number of ways including but not limited to integral methods, analytical, finite element, finite difference, finite volume, Monte Carlo and multi-grid techniques. The limitations of analytically derived solutions such as Fourier series expansion (as exemplified by (2)) with simplified boundary conditions, using well known separation of variables method for solving the heat equations in 3D is limited in its ability to solve interconnect temperatures as the simplified
                              T          ⁡                      (                          x              ,              y              ,              z                        )                          =                              ∑                          i              =              0                        ∞                    ⁢                                          ⁢                                    ∑                              j                =                0                            ∞                        ⁢                                                  ⁢                                          sin                ⁢                                                      i                    ⁢                                                                                  ⁢                    πλ                                    a                                ⁢                                                                  ⁢                sin                ⁢                                                      j                    ⁢                                                                                  ⁢                    πλ                                    a                                ⁢                                                                  ⁢                cos                ⁢                                                      i                    ⁢                                                                                  ⁢                    π                    ⁢                                                                                  ⁢                    x                                    a                                ⁢                                                                  ⁢                cos                ⁢                                                      j                    ⁢                                                                                  ⁢                    π                    ⁢                                                                                  ⁢                    y                                    a                                ⁢                                                                  ⁢                sinh                ⁢                                                                                                                              i                          2                                                +                                                                              j                            2                                                    ⁢                          π                          ⁢                                                                                                          ⁢                          z                                                                    a                                                        a                                                                              (                                      1                    +                                          δ                      ⁢                                                                                          ⁢                      i                                                        )                                ⁢                i                ⁢                                                                  ⁢                                  π                  ⁡                                      (                                          1                      +                                              δ                        ⁢                                                                                                  ⁢                        j                                                              )                                                  ⁢                j                ⁢                                                                  ⁢                π                ⁢                                                                                                                              i                          2                                                +                                                  j                          2                                                                                      ⁢                    π                    ⁢                                                                                  ⁢                    d                                    a                                ⁢                                                                  ⁢                cosh                ⁢                                                                                                                              i                          2                                                +                                                  j                          2                                                                                      ⁢                    π                    ⁢                                                                                  ⁢                    d                                    a                                                                                        (        2        )            
Assumptions on boundary conditions do not adequately account for the interconnect temperature contributions by the aggressor to its thermally coupled victims; if realistic boundary conditions were to be set up it would make the solution unwieldy and excessively time-consuming for interconnect structures in real-life examples of IC and stacked chip designs. Mesh based thermal solvers on the other hand provide the accuracy needed by electro-thermal and electro-mechanical analysis but they are computationally prohibitively time-consuming when applied to very large semiconductor chip designs with billions of shapes representing interconnects, and sometimes capacity limited, or limited in their ability to model the details of the heat transfer paths in full chip and chip-package systems, non-linear effects caused by size of interconnects that are in the nanometer range may need iterations on the solutions and add to the runtimes of solvers. Alternative methods with simplified models of the ILD (interlayer dielectric) have been reported. As examples of such methods one example assumes simplified boundary conditions of the system; in another example the heat conduction paths are modeled with equation based equivalent thermal conductivity. In cases where a simplified conductivity model is used for the ILDs the mesh based solver run times will continue to grow by the large number of mesh points whether the solver works on a per layer basis or over the entire chip thereby making it impossible to obtain a scalable solution.
Accordingly, there exists a need for improved method and apparatus for determining thermal values for interconnects, and particularly for large numbers of interconnects within chips and/or between chips that function together in a unit or package to provide improved IC design.